1. Field of the Invention
The present invention relates to instruction buffer control in a processor, and particularly relates to an instruction buffer controller which enables speedy re-fetching of instructions.
2. DESCRIPTION OF THE PRIOR ART
Conventionally, a processor generally prefetches instructions stored in the main storage and stores them in the instruction buffer so that it can fetch the instruction to be executed from the instruction buffer. Such instruction fetching using a buffer capable of processing at a speed higher than the main storage realizes improved speed of processing. When an instruction is fetched from the instruction buffer and then issued to the instruction execution section, the instruction buffer is controlled so as to drive out the applicable instruction.
Thus, in conventional control of an instruction buffer, an instruction once fetched from the instruction buffer is removed from the instruction buffer. Therefore, if an interruption occurs during execution of an instruction, there may be a problem: when executing again the instruction which was being executed after processing of the interruption, that instruction already driven out of the instruction buffer cannot be fetched from the buffer and must be obtained from the main storage. It requires a longer time until completion of instruction execution than a case where the instruction is fetched from the instruction buffer.
Besides, a branch instruction for branching to the address of the instruction which has been completed causes a program loop where the same instruction is repeated, which requires re-fetching of the completed instruction. In this case, too, since the instruction once fetched and executed is driven out of the instruction buffer, that instruction must be transferred from the main storage for execution of that instruction again. The time required for re-fetching of the instruction impedes speedy execution of the instruction.